This invention relates to a semiconductor device, and more specifically to such having formed a fully depleted MISFET (metal insulator semiconductor field effect transistor) on a semiconductor layer stacked on a support substrate via an insulating film.
A FET made of an SOI (silicon on insulator), which is a semiconductor layer on an insulating substrate, is remarked as a hopeful device for application to a low-consumption device or a high-speed circuit such as high-speed CPU because its source-drain parasitic capacitance can be reduced much smaller than that of FET made on a bulk semiconductor substrate. Especially when the thickness of the SOI film as the semiconductor layer is reduced smaller than the thickness of the depletion layer of the channel region, the channel region can be fully depleted. As a result, it can remove or prevent unfavorable phenomena such as kink characteristics and current overshoot effect which are involved in FETs made by using a semiconductor layer thicker than the depletion layer.
The transistor in which the entire channel region can be carrier-freed (hereinafter called "fully depleted transistor") also has other various advantages, such as prevention of short-channel effect, improvement in punch-through resistance, improvement in sub-threshold coefficient, increase of the channel mobility, and so on.
The complete depletion transistor, however, involves the problem that the threshold value fluctuates due to the fluctuation in the impurity concentration of the semiconductor layer in the channel region or the fluctuation in the thickness of the SOI film which may caused by the changes of the process conditions, for example.
A method for treating the problems caused by changes of the process conditions is disclosed, for example, in Japanese Patent Laid-open Publication No. H9-312401, in which a back gate is provided on the support substrate under the insulating layer under the SOI layer, and the threshold value is controlled by changing the voltage to be applied to the back gate between the operative mode and the standby mode.
In this method, however, the back gate voltage is determined regardless of fluctuation in thickness of the SOI film and concentration of the substrate. And, nothing has been disclosed on specific means or construction for applying the back gate voltage so as to minimize the threshold value sensitivity to fluctuation of the thickness of the SOI film, for example.
More specifically, in the method and construction for reducing the threshold value sensitivity to in the conventional fully depleted transistor, the relationship of the back gate voltage, the optimum value of the SOI film thickness and the impurity concentration have not been taken into consideration. Therefore, it has been difficult to fix the threshold value to a regulated value and to decrease the threshold value sensitivity to fluctuation in the SOI layer thickness and impurity concentration.